module Spread(Clk, BPSK, Doubled_BPSK, DemodIn, Early, Late, Dithered_PRBS, Punctual_PRBS, DemodOut, LED);
input Clk, BPSK, Doubled_BPSK, DemodIn;
output Early, Late, Dithered_PRBS, Punctual_PRBS, DemodOut, LED;

reg Early, Late, Half_Chip, Dithered_PRBS, Carrier;
reg [6:0] Shift;
reg [1:0] Dither;
wire DemodOut;
reg Prev0, Prev1, LED;
reg [9:0] Width;
reg [9:0] Total;

assign Punctual_PRBS = Shift[6];

assign DemodOut = BPSK ^ Carrier;

always @ (negedge Doubled_BPSK) Carrier <= ~Carrier;

always @ (posedge Clk)
begin
	Prev0 <= DemodIn;
	Prev1 <= Prev0;
	if (Prev0 == Prev1) begin
		if (~&Width) Width <= Width + 1;
		if (~&Total) Total <= Total + 1;
	end else begin
		Width <= 0;
		if (Width<64) Total <= 0;
	end 	
	LED <= &Total;
	
	Half_Chip <= ~Half_Chip;
	
	if (Half_Chip)
	begin
		if (Shift == 7'b0000001)
		begin
			Dither <= Dither + 1;
			Early <= (Dither==2);
			Late <= (Dither==0);

		end
		Dithered_PRBS <= Dither[1]? Shift[5] : Shift[6];
	end else begin
		Shift[6:1] <= Shift[5:0];
		if (|Shift) Shift[0] <= Shift[5] ^ Shift[6];
		else Shift[0] <= 1'b1;
	end
end

endmodule