`define PRE_BITS    6
`define ROW_BITS    5
`define COL_BITS    3

module Stab (VCO, REF, OUT, D, A, OE_NL, OE_NH, WE_N);

input           VCO;
input           REF;
output reg      OUT;

inout    [7:0]  D;
output  [10:0]  A;

output          OE_NL;
output          OE_NH;
output          WE_N;

reg        sync_ref, we;
reg  [7:0] byte;

reg [`PRE_BITS+`ROW_BITS+`COL_BITS-1:0] count;

wire [`ROW_BITS-1:0] row;
wire           [2:0] col;
 
wire pwr, gnd, oel, oeh;

bufif1 b0 (D[0], byte[0], oeh);
bufif1 b1 (D[1], byte[1], oeh);
bufif1 b2 (D[2], byte[2], oeh);
bufif1 b3 (D[3], byte[3], oeh);
bufif1 b4 (D[4], byte[4], oeh);
bufif1 b5 (D[5], byte[5], oeh);
bufif1 b6 (D[6], byte[6], oeh);
bufif1 b7 (D[7], byte[7], oeh);

bufif1 bL (OE_NL, gnd, oel);
bufif1 bH (OE_NH, pwr, oeh);

LCELL lc_pwr (1, pwr);
LCELL lc_gnd (0, gnd);

LCELL lc_oel (~count[`PRE_BITS-1], oel);
LCELL lc_oeh ( count[`PRE_BITS-1], oeh);

assign row =  count[`PRE_BITS+`ROW_BITS          -1:`PRE_BITS          ];
assign col =  count[`PRE_BITS+`ROW_BITS+`COL_BITS-1:`PRE_BITS+`ROW_BITS];

assign A[`ROW_BITS-1:0] = row;
assign A[10: `ROW_BITS] = 0;

assign WE_N = ~we || VCO;

always @ (posedge VCO) begin
    count <= count + 1'b1;
        
    we <= oel & (&count[`PRE_BITS-2:0]);

    if (&count[`PRE_BITS-2:0]) begin
        if (oeh) begin
            sync_ref <= REF;
        end else begin
            byte[0] <= col==3'd0 ? sync_ref : D[0];
            byte[1] <= col==3'd1 ? sync_ref : D[1];
            byte[2] <= col==3'd2 ? sync_ref : D[2];
            byte[3] <= col==3'd3 ? sync_ref : D[3];
            byte[4] <= col==3'd4 ? sync_ref : D[4];
            byte[5] <= col==3'd5 ? sync_ref : D[5];
            byte[6] <= col==3'd6 ? sync_ref : D[6];
            byte[7] <= col==3'd7 ? sync_ref : D[7];
            
            case (col)
                3'd0:   OUT <= sync_ref ^ D[0];
                3'd1:   OUT <= sync_ref ^ D[1];
                3'd2:   OUT <= sync_ref ^ D[2];
                3'd3:   OUT <= sync_ref ^ D[3];
                3'd4:   OUT <= sync_ref ^ D[4];
                3'd5:   OUT <= sync_ref ^ D[5];
                3'd6:   OUT <= sync_ref ^ D[6];
                3'd7:   OUT <= sync_ref ^ D[7];
            endcase         
        end
    end
end

endmodule