module Stab(VCO, REF, OUT);
input VCO, REF;
output OUT;

`define COUNT_LEN 9
`define SHIFT_LEN 50

reg [`COUNT_LEN-1:0] Count;
reg [`SHIFT_LEN-1:0] Shift;
reg Sample;

assign OUT = Shift[`SHIFT_LEN-1] ^ Sample;

always @ (posedge VCO)
begin
    Count <= Count + 1'b1;
    if (Count==0) begin
        Sample <= REF;
        Shift[`SHIFT_LEN-1:0] <= {Shift[`SHIFT_LEN-2:0], Sample};
    end
end

endmodule